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Chapter 1: Cyclone III Device Datasheet
1–17
Switching Characteristics
Table 1–24 lists the active configuration mode specifications for Cyclone III devices.
Table 1–24. Cyclone III Devices Active Configuration Mode Specifications
Programming Mode
Active Parallel (AP)
Active Serial (AS)
DCLK Range
20 – 40
20 – 40
Unit
MHz
MHz
Table 1–25 lists the JTAG timing parameters and values for Cyclone III devices.
Table 1–25. Cyclone III Devices JTAG Timing Parameters
(1)
Symbol
t JCP
t JCH
t JCL
t JPSU_TDI
Parameter
TCK clock period
TCK clock high time
TCK clock low time
JTAG port setup time for TDI
Min
40
20
20
1
Max
—
—
—
—
Unit
ns
ns
ns
ns
t JPSU_TMS JTAG port setup time for TMS
3
—
ns
t JPH
JTAG port hold time
10
—
ns
t JPCO
JTAG port clock to
output (2)
—
15
ns
t JPZX
JTAG port high impedance to valid
output (2)
—
15
ns
t JPXZ
JTAG port valid output to high
impedance (2)
—
15
ns
t JSSU
t JSH
t JSCO
t JSZX
t JSXZ
Capture register setup time
Capture register hold time
Update register clock to output
Update register high impedance to valid output
Update register valid output to high impedance
5
10
—
—
—
—
—
25
25
25
ns
ns
ns
ns
ns
Notes to Table 1–25 :
(1) For more information about JTAG waveforms, refer to “JTAG Waveform” in “Glossary” on page 1–27 .
(2) The specification is shown for 3.3-, 3.0-, and 2.5-V LVTTL/LVCMOS operation of JTAG pins. For 1.8-V LVTTL/LVCMOS
and 1.5-V LVCMOS, the JTAG port clock to output time is 16 ns.
Periphery Performance
This section describes periphery performance, including high-speed I/O, external
memory interface, and IOE programmable delay.
I/O performance supports several system interfacing, for example, the high-speed
I/O interface, external memory interface, and the PCI/PCI-X bus interface. I/O using
the SSTL-18 Class I termination standard can achieve up to the stated DDR2 SDRAM
interfacing speeds with typical DDR SDRAM memory interface setup. I/O using
general-purpose I/O standards such as 3.0-, 2.5-, 1.8-, or 1.5-LVTTL/LVCMOS are
capable of a typical 200 MHz interfacing frequency with a 10 pF load.
1
Actual achievable frequency depends on design- and system-specific factors. Perform
HSPICE/IBIS simulations based on your specific design and system setup to
determine the maximum achievable frequency in your system.
July 2012
Altera Corporation
Cyclone III Device Handbook
Volume 2
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